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                <h3 class="panel-title"> CACHECTRL Register Index</h3>
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                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000000:</span>
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                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CACHECFG" target="_self">CACHECFG - Flash Cache Control Register</a>
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                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000004:</span>
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                            <a class="el" href="#FLASHCFG" target="_self">FLASHCFG - Flash Control Register</a>
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                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000008:</span>
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                            <a class="el" href="#CTRL" target="_self">CTRL - Cache Control</a>
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                            <span class="h5">0x00000010:</span>
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                            <a class="el" href="#NCR0START" target="_self">NCR0START - Flash Cache Noncachable Region 0 Start</a>
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                            <span class="h5">0x00000014:</span>
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                            <a class="el" href="#NCR0END" target="_self">NCR0END - Flash Cache Noncachable Region 0 End</a>
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                            <span class="h5">0x00000018:</span>
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                            <a class="el" href="#NCR1START" target="_self">NCR1START - Flash Cache Noncachable Region 1 Start</a>
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                            <span class="h5">0x0000001C:</span>
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                            <a class="el" href="#NCR1END" target="_self">NCR1END - Flash Cache Noncachable Region 1 End</a>
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                            <span class="h5">0x00000040:</span>
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                            <a class="el" href="#DMON0" target="_self">DMON0 - Data Cache Total Accesses</a>
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                            <span class="h5">0x00000044:</span>
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                            <a class="el" href="#DMON1" target="_self">DMON1 - Data Cache Tag Lookups</a>
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                            <span class="h5">0x00000048:</span>
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                            <a class="el" href="#DMON2" target="_self">DMON2 - Data Cache Hits</a>
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                            <span class="h5">0x0000004C:</span>
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                            <a class="el" href="#DMON3" target="_self">DMON3 - Data Cache Line Hits</a>
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                            <span class="h5">0x00000050:</span>
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                            <a class="el" href="#IMON0" target="_self">IMON0 - Instruction Cache Total Accesses</a>
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                            <span class="h5">0x00000054:</span>
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                            <a class="el" href="#IMON1" target="_self">IMON1 - Instruction Cache Tag Lookups</a>
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                            <span class="h5">0x00000058:</span>
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                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#IMON2" target="_self">IMON2 - Instruction Cache Hits</a>
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                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000005C:</span>
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                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#IMON3" target="_self">IMON3 - Instruction Cache Line Hits</a>
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        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CACHECFG" class="panel-title">CACHECFG - Flash Cache Control Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40018000</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Flash Cache Control Register</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="7">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">ENABLE_MONITOR
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DATA_CLKGATE
                                <br>0x1</td>

                            <td align="center" colspan="8">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">CACHE_LS
                                <br>0x1</td>

                            <td align="center" colspan="1">CACHE_CLKGATE
                                <br>0x1</td>

                            <td align="center" colspan="1">DCACHE_ENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">ICACHE_ENABLE
                                <br>0x0</td>

                            <td align="center" colspan="4">CONFIG
                                <br>0x5</td>

                            <td align="center" colspan="1">ENABLE_NC1
                                <br>0x0</td>

                            <td align="center" colspan="1">ENABLE_NC0
                                <br>0x0</td>

                            <td align="center" colspan="1">LRU
                                <br>0x0</td>

                            <td align="center" colspan="1">ENABLE
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:25</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>ENABLE_MONITOR</td>
                            <td>RW</td>
                            <td>Enable Cache Monitoring Stats.  Cache monitoring consumes additional power and should only be enabled when profiling code and counters will increment when this bit is set.  Counter values will be retained when this is set to 0, allowing software to enable/disable counting for multiple code segments.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23:21</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>20</td>
                            <td>DATA_CLKGATE</td>
                            <td>RW</td>
                            <td>Enable aggressive clock gating of entire data array.  This bit should be set to 1 for optimal power efficiency.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>19:12</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>CACHE_LS</td>
                            <td>RW</td>
                            <td>Enable LS (light sleep) of cache RAMs.  Software should DISABLE this bit since cache activity is too high to benefit from LS usage.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>CACHE_CLKGATE</td>
                            <td>RW</td>
                            <td>Enable clock gating of cache TAG RAM.  Software should enable this bit for optimal power efficiency.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>DCACHE_ENABLE</td>
                            <td>RW</td>
                            <td>Enable Flash Data Caching.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>ICACHE_ENABLE</td>
                            <td>RW</td>
                            <td>Enable Flash Instruction Caching<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:4</td>
                            <td>CONFIG</td>
                            <td>RW</td>
                            <td>Sets the cache configuration<br><br>
                                 W1_128B_512E         = 0x4 - Direct mapped, 128-bit linesize, 512 entries (4 SRAMs active)<br>
                             W2_128B_512E         = 0x5 - Two-way set associative, 128-bit linesize, 512 entries (8 SRAMs active)<br>
                             W1_128B_1024E        = 0x8 - Direct mapped, 128-bit linesize, 1024 entries (8 SRAMs active)</td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>ENABLE_NC1</td>
                            <td>RW</td>
                            <td>Enable Non-cacheable region 1.  See NCR1 registers to define the region.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>ENABLE_NC0</td>
                            <td>RW</td>
                            <td>Enable Non-cacheable region 0.  See NCR0 registers to define the region.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>LRU</td>
                            <td>RW</td>
                            <td>Sets the cache repleacment policy.  0=LRR (least recently replaced), 1=LRU (least recently used).  LRR minimizes writes to the TAG SRAM.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>ENABLE</td>
                            <td>RW</td>
                            <td>Enables the flash cache controller and enables power to the cache SRAMs.  The ICACHE_ENABLE and DCACHE_ENABLE should be set to enable caching for each type of access.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FLASHCFG" class="panel-title">FLASHCFG - Flash Control Register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40018004</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Flash Control Register</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="18">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="2">LPMMODE
                                <br>0x0</td>

                            <td align="center" colspan="4">LPM_RD_WAIT
                                <br>0x8</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="3">SEDELAY
                                <br>0x7</td>

                            <td align="center" colspan="4">RD_WAIT
                                <br>0x3</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:14</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>13:12</td>
                            <td>LPMMODE</td>
                            <td>RW</td>
                            <td>Controls flash low power modes (control of LPM pin).<br><br>
                                 NEVER                = 0x0 - High power mode (LPM not used).<br>
                             STANDBY              = 0x1 - Fast Standby mode.  LPM deasserted for read operations, but asserted while flash IDLE.<br>
                             ALWAYS               = 0x2 - Low Power mode.  LPM always asserted for reads.  LPM_RD_WAIT must be programmed to accomodate longer read access times.</td>
                        </tr>

                        <tr>
                            <td>11:8</td>
                            <td>LPM_RD_WAIT</td>
                            <td>RW</td>
                            <td>Sets flash waitstates when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>6:4</td>
                            <td>SEDELAY</td>
                            <td>RW</td>
                            <td>Sets SE delay (flash address setup).  A value of 5 is recommended.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3:0</td>
                            <td>RD_WAIT</td>
                            <td>RW</td>
                            <td>Sets read waitstates for normal (fast) operation.  A value of 1 is recommended.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CTRL" class="panel-title">CTRL - Cache Control</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40018008</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Cache Control</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="21">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">FLASH1_SLM_ENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">FLASH1_SLM_DISABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">FLASH1_SLM_STATUS
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">FLASH0_SLM_ENABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">FLASH0_SLM_DISABLE
                                <br>0x0</td>

                            <td align="center" colspan="1">FLASH0_SLM_STATUS
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">CACHE_READY
                                <br>0x0</td>

                            <td align="center" colspan="1">RESET_STAT
                                <br>0x0</td>

                            <td align="center" colspan="1">INVALIDATE
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:11</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>FLASH1_SLM_ENABLE</td>
                            <td>WO</td>
                            <td>Enable Flash Sleep Mode.  Write to 1 to put flash 1 into sleep mode.  NOTE: there is a 5us latency after waking flash until the first access will be returned.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>FLASH1_SLM_DISABLE</td>
                            <td>WO</td>
                            <td>Disable Flash Sleep Mode.  Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it).<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>FLASH1_SLM_STATUS</td>
                            <td>RO</td>
                            <td>Flash Sleep Mode Status.  1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>FLASH0_SLM_ENABLE</td>
                            <td>WO</td>
                            <td>Enable Flash Sleep Mode.  Write to 1 to put flash 0 into sleep mode.  NOTE: there is a 5us latency after waking flash until the first access will be returned.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>FLASH0_SLM_DISABLE</td>
                            <td>WO</td>
                            <td>Disable Flash Sleep Mode.  Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it).<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>FLASH0_SLM_STATUS</td>
                            <td>RO</td>
                            <td>Flash Sleep Mode Status.  1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>CACHE_READY</td>
                            <td>RO</td>
                            <td>Cache Ready Status (enabled and not processing an invalidate operation)<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>RESET_STAT</td>
                            <td>WO</td>
                            <td>Reset Cache Statistics.  When written to a 1, the cache monitor counters will be cleared.  The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set.<br><br>
                                 CLEAR                = 0x1 - Clear Cache Stats</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>INVALIDATE</td>
                            <td>WO</td>
                            <td>Writing a 1 to this bitfield invalidates the flash cache contents.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="NCR0START" class="panel-title">NCR0START - Flash Cache Noncachable Region 0 Start</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40018010</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Flash Cache Noncachable Region 0 Start</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="5">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="23">ADDR
                                <br>0x0</td>

                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:27</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26:4</td>
                            <td>ADDR</td>
                            <td>RW</td>
                            <td>Start address for non-cacheable region 0<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3:0</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="NCR0END" class="panel-title">NCR0END - Flash Cache Noncachable Region 0 End</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40018014</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Flash Cache Noncachable Region 0 End</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="5">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="23">ADDR
                                <br>0x0</td>

                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:27</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26:4</td>
                            <td>ADDR</td>
                            <td>RW</td>
                            <td>End address for non-cacheable region 0<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3:0</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="NCR1START" class="panel-title">NCR1START - Flash Cache Noncachable Region 1 Start</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40018018</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Flash Cache Noncachable Region 1 Start</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="5">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="23">ADDR
                                <br>0x0</td>

                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:27</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26:4</td>
                            <td>ADDR</td>
                            <td>RW</td>
                            <td>Start address for non-cacheable region 1<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3:0</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="NCR1END" class="panel-title">NCR1END - Flash Cache Noncachable Region 1 End</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x4001801C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Flash Cache Noncachable Region 1 End</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="5">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="23">ADDR
                                <br>0x0</td>

                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:27</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26:4</td>
                            <td>ADDR</td>
                            <td>RW</td>
                            <td>End address for non-cacheable region 1<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3:0</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>This bitfield is reserved for future use.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="DMON0" class="panel-title">DMON0 - Data Cache Total Accesses</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40018040</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Data Cache Total Accesses</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">DACCESS_COUNT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>DACCESS_COUNT</td>
                            <td>RO</td>
                            <td>Total accesses to data cache.  All performance metrics should be relative to the number of accesses performed.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="DMON1" class="panel-title">DMON1 - Data Cache Tag Lookups</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40018044</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Data Cache Tag Lookups</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">DLOOKUP_COUNT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>DLOOKUP_COUNT</td>
                            <td>RO</td>
                            <td>Total tag lookups from data cache.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="DMON2" class="panel-title">DMON2 - Data Cache Hits</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40018048</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Data Cache Hits</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">DHIT_COUNT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>DHIT_COUNT</td>
                            <td>RO</td>
                            <td>Cache hits from lookup operations.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="DMON3" class="panel-title">DMON3 - Data Cache Line Hits</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x4001804C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Data Cache Line Hits</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">DLINE_COUNT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>DLINE_COUNT</td>
                            <td>RO</td>
                            <td>Cache hits from line cache<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="IMON0" class="panel-title">IMON0 - Instruction Cache Total Accesses</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40018050</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Instruction Cache Total Accesses</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">IACCESS_COUNT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>IACCESS_COUNT</td>
                            <td>RO</td>
                            <td>Total accesses to Instruction cache<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="IMON1" class="panel-title">IMON1 - Instruction Cache Tag Lookups</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40018054</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Instruction Cache Tag Lookups</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">ILOOKUP_COUNT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>ILOOKUP_COUNT</td>
                            <td>RO</td>
                            <td>Total tag lookups from Instruction cache<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="IMON2" class="panel-title">IMON2 - Instruction Cache Hits</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x40018058</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Instruction Cache Hits</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">IHIT_COUNT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>IHIT_COUNT</td>
                            <td>RO</td>
                            <td>Cache hits from lookup operations<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="IMON3" class="panel-title">IMON3 - Instruction Cache Line Hits</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x4001805C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Instruction Cache Line Hits</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...</span>
AM_REGVAL(0x50010000) = 0x1234;              <span style='color:#3f7f59; '>// by address.</span>
ADC-&gt;CFG = 0x1234;                           <span style='color:#3f7f59; '>// by structure pointer.</span>
ADCn(0)-&gt;CFG = 0x1234;                       <span style='color:#3f7f59; '>// by structure pointer (with instance number).</span>

<span style='color:#3f7f59; '>// Changing the ADC clock...</span>
ADCn(0)-&gt;CFG_b.CLKSEL = 0x2;                 <span style='color:#3f7f59; '>// by raw value.</span>
ADCn(0)-&gt;CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; <span style='color:#3f7f59; '>// using an enumerated value.</span></pre>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">ILINE_COUNT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>ILINE_COUNT</td>
                            <td>RO</td>
                            <td>Cache hits from line cache<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

    </body>

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        <div id="footer" align="right">
            <small>
                AmbiqSuite Register Documentation&nbsp;
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                <img class="footer" src="../resources/ambiqmicro_logo.png" alt="Ambiq Micro"/></a>&nbsp&nbsp Copyright &copy; 2020&nbsp&nbsp<br />
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